Class-D amplifiers serve as audio power amplifiers. The class-D amplifiers amplify electric power by switching, and are structured, for example, as shown in FIG. 10.
More specifically, a digital audio signal Pin is sent through an input terminal Tin to PWM (pulse width modulation) modulation circuits 11 and 12, and the input signal Pin is converted to a pair of PWM signals PA and PB.
In this case, the pulse widths of the PWM signals PA and PB are changed according to the level (the level of each sample of the original analog signal converted to the signal Pin) indicated by the input signal Pin. As shown in FIG. 12, the pulse width of one PWM signal PA has a magnitude corresponding to the level indicated by the input signal Pin, and the pulse width of the other PWM signal PB has a magnitude corresponding to the two's complement of the level indicated by the input signal Pin. In the PWM signals PA and PB, their rising edges are fixed to the start point of one cycle period (reference period) Tc of the PWM signals PA and PB, and their falling edges are shifted according to the level indicated by the input signal Pin.
The carrier frequency fc (=1/Tc) of the PWM signals PA and PB is set, for example, to 16 times the sampling frequency fs of the input digital audio signal Pin. When fs is 48 kHz, fc=16 fs=16×48 kHz=768 kHz.
Such a PWM signal PA is sent to a drive circuit 13, and a pair of drive voltages +PA and −PA which are the signal PA and a signal having the same level as the signal PA with the inverted polarities is formed as shown in FIG. 11A. These drive voltages +PA and −PA are sent to the gates of a pair of n-channel MOS-FETs (metal oxide semiconductor type field effect transistors) (Q11 and Q12). In this case, the FETs (Q11 and Q12) constitute a push-pull circuit 15. The drain of the FET (Q11) is connected to a power-supply terminal TPWR, the source of the FET (Q11) is connected to the drain of the FET (Q12), and the source of the FET (Q12) is connected to the ground. To the power-supply terminal TPWR, a stable DC voltage +VDD is supplied as a power-supply voltage. The voltage +VDD ranges, for example, from 20 V to 50 V.
The source of the FET (Q11) and the drain of the FET (Q12) are connected to one end of a speaker 19 through a low-pass filter 17 formed of a coil and a capacitor.
The PWM signal PB sent from the PWM modulation circuit 11 also passes through in the same way as the PWM signal PA. More specifically, the PWM signal PB is sent to a drive circuit 14, and a pair of drive voltages +PB and −PB which are the signal PB and a signal having the same level as the signal PB with the inverted polarities is formed as shown in FIG. 11B. These drive voltages +PB and −PB are sent to the gates of a pair of n-channel MOS-FETs (Q13 and Q14) constituting a push-pull circuit 16.
The source of the FET (Q13) and the drain of the FET (Q14) are connected to the other end of the speaker 19 through a low-pass filter 18 formed of a coil and a capacitor.
Therefore, when +PA=“H”, −PA=“L”, the FET (Q11) is turned on, and the FET (Q12) is turned off. Consequently, a voltage VA generated at the connection point of the FETs (Q11 and Q12) is the voltage +VDD, as shown in FIG. 1C. Conversely, when +PA=“L”, −PA=“H”, the FET (Q11) is turned off, and the FET (Q12) is turned on. Consequently, VA=0.
In the same way, when +PB=“H”, −PB=“L”, the FET (Q13) is turned on, and the FET (Q14) is turned off. Consequently, a voltage VB generated at the connection point of the FETs (Q13 and Q14) is the voltage +VDD, as shown in FIG. 11D. Conversely, when +PB=“L”, −PB=“H”, the FET (Q13) is turned off, and the FET (Q14) is turned on. Consequently, VB=0.
In a period when VA=+VDD and VB=0, as shown in FIG. 10 and FIG. 11E, current “i” flows from the connection point of the FETs (Q11 and Q12) to the connection point of the FETs (Q13 and Q14) through a line from the low-pass filter 17 through the speaker 19 to the low-pass filter 18.
In a period when VA=0 and VB=+VDD, the current “i” flows from the connection point of the FETs (Q13 and Q14) to the connection point of the FETs (Q11 and Q12) through a line from the low-pass filter 18 through the speaker 19 to the low-pass filter 17, in the direction reverse to that shown in FIG. 10. In a period when VA=VB=+VDD and in a period when VA=VB=0, the current “i” does not flow. In other words, the push-pull circuits 15 and 16 form a BTL (bridged-tied load) circuit.
The periods when the current “i” flows is changed according to the periods when the original PWM signals PA and PB are at “H”. When the current “i” flows through the speaker 19, the current “i” is integrated by the low-pass filters 17 and 18. As a result, the current “i” flowing through the speaker 19 is the analog current which corresponds to the level indicated by the input signal Pin and of which the electric power has been amplified. In other words, the electric-power-amplified output is sent to the speaker 19.
The circuit shown in FIG. 10 functions as a power amplifier in this way. The FETs (Q11 to Q14) switch the power-supply voltage +VDD according to the input digital audio signal Pin to amplify the electric power. Therefore, a high efficiency and a large output are obtained.
Since the above-described power amplifier switches the power-supply voltage +VDD at a high speed to generate the output voltages VA and VB, as also shown in FIG. 11C and FIG. 11D, extraneous emission occurs at the rising edges and the falling edges of the output voltages VA and VB. In addition, when switching is achieved, since the power-supply voltage +VDD is as high as, for example, 20 V to 50 V, its emission level is quite high. The carrier frequency Fc of the PWM signals PA and PB is, for example, 768 kHz as in the above case, and is included in the band of medium-wave broadcasting.
Therefore, when a class-D power amplifier such as that described above is integrated with a receiver as in car audio systems or is disposed close to a receiver, emission caused at the rising edges and the falling edges of the output voltages VA and VB disturbs broadcasting receiving. Since the rising edges and the falling edges of the output voltages VA and VB are steep and include many harmonics, the harmonics are also emitted, which may disturb receiving at FM receivers and TV receivers.
An object of the present invention is to provide a power amplifier having a reduced level of such emission.